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HPCA
1998
IEEE
15 years 2 months ago
The Potential for Using Thread-Level Data Speculation to Facilitate Automatic Parallelization
As we look to the future, and the prospect of a billion transistors on a chip, it seems inevitable that microprocessors will exploit having multiple parallel threads. To achieve t...
J. Gregory Steffan, Todd C. Mowry
DSD
2009
IEEE
160views Hardware» more  DSD 2009»
15 years 1 months ago
Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple Processors
Voltage-frequency scaling (VFS) trades a linear processor slowdown for a potentially quadratic reduction in energy consumption. Complex dependencies may exist between different tas...
Anca Mariana Molnos, Kees Goossens
DAC
2004
ACM
15 years 10 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
DAC
2006
ACM
15 years 10 months ago
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...
Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil...
DATE
2006
IEEE
87views Hardware» more  DATE 2006»
15 years 3 months ago
Supporting task migration in multi-processor systems-on-chip: a feasibility study
With the advent of multi-processor systems-on-chip, the interest in process migration is again on the rise both in research and in product development. New challenges associated w...
Stefano Bertozzi, Andrea Acquaviva, Davide Bertozz...