With the shift to many-core chip multiprocessors (CMPs), a critical issue is how to effectively coordinate and manage the execution of applications and hardware resources to overc...
Wei Wang, Tanima Dey, Ryan W. Moore, Mahmut Aktaso...
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
When designing heterogeneous MP-SoCs designers have to take into account various objectives such as power, die size, flexibility, performance or programmability. But to be able t...
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
As increasing the performance of single-threaded processors becomes increasingly difficult, consumer desktop processors are moving toward multi-core designs. One way to enhance th...