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» Application mapping for chip multiprocessors
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DATE
2003
IEEE
176views Hardware» more  DATE 2003»
15 years 11 months ago
Hardware/Software Partitioning of Operating Systems
As MultiProcessor System-on-a-Chip (MPSoC) designs become more common, hardware/software codesign engineers face new challenges involving operating system integration. To speed up...
Vincent John Mooney
EUROPAR
2006
Springer
15 years 9 months ago
PAM-SoC: A Toolchain for Predicting MPSoC Performance
In the past, research on Multiprocessor Systems-on-Chip (MPSoC) has focused mainly on increasing the available processing power on a chip, while less effort was put into specific s...
Ana Lucia Varbanescu, Henk J. Sips, Arjan J. C. va...
ASAP
2005
IEEE
169views Hardware» more  ASAP 2005»
15 years 11 months ago
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a li...
Grigoris Dimitroulakos, Michalis D. Galanis, Costa...
ISCA
2003
IEEE
183views Hardware» more  ISCA 2003»
15 years 11 months ago
The Jrpm System for Dynamically Parallelizing Java Programs
We describe the Java runtime parallelizing machine (Jrpm), a complete system for parallelizing sequential programs automatically. Jrpm is based on a chip multiprocessor (CMP) with...
Michael K. Chen, Kunle Olukotun
HPCA
1996
IEEE
15 years 10 months ago
Fault-Tolerance with Multimodule Routers
The current multiprocessors such asCray T3D support interprocessor communication using partitioned dimension-order routers (PDRs). In a PDR implementation, the routing logic and sw...
Suresh Chalasani, Rajendra V. Boppana