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» Application mapping for chip multiprocessors
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2006
IEEE
14 years 11 months ago
Efficient computation of buffer capacities for multi-rate real-time systems with back-pressure
A key step in the design of multi-rate real-time systems is the determination of buffer capacities. In our multi-processor system, we apply back-pressure as caused by bounded buff...
Maarten Wiggers, Marco Bekooij, Pierre G. Jansen, ...
ASAP
2004
IEEE
101views Hardware» more  ASAP 2004»
15 years 1 months ago
Register Organization for Enhanced On-Chip Parallelism
Large register file with multiple ports is a critical component of a high-performance processor. A large number of registers are necessary for processing a larger number of in-fli...
Rama Sangireddy
70
Voted
DATE
2006
IEEE
154views Hardware» more  DATE 2006»
15 years 3 months ago
An integrated open framework for heterogeneous MPSoC design space exploration
In recent years, increasing manufacturing density has allowed the development of Multi-Processor Systems-on-Chip (MPSoCs). Application-Specific Instruction Set Processors (ASIPs)...
Federico Angiolini, Jianjiang Ceng, Rainer Leupers...
86
Voted
IPPS
2006
IEEE
15 years 3 months ago
Enhancing L2 organization for CMPs with a center cell
Chip multiprocessors (CMPs) are becoming a popular way of exploiting ever-increasing number of on-chip transistors. At the same time, the location of data on the chip can play a c...
Chun Liu, Anand Sivasubramaniam, Mahmut T. Kandemi...
GECCO
2010
Springer
233views Optimization» more  GECCO 2010»
15 years 2 months ago
Evolutionary-based conflict-free scheduling of collective communications on spidergon NoCs
The Spidergon interconnection network has become popular recently in multiprocessor systems on chips. To the best of our knowledge, algorithms for collective communications (CC) h...
Jirí Jaros, Vaclav Dvorak