422 search results - page 58 / 85 » Application mapping for chip multiprocessors |
ASPLOS
2008
ACM
14 years 11 months ago
2008
ACM
Parallel and concurrent garbage collectors are increasingly employed by managed runtime environments (MREs) to maintain scalability, as multi-core architectures and multi-threaded...
IJCAI
1997
14 years 11 months ago
1997
This paper describes an evolvable hardware (EHW) system for generalized neural network learning. We have developed an ASIC VLSI chip, which is a building block to configure a scal...
100
click to vote
VLSID
2004
IEEE
15 years 10 months ago
2004
IEEE
As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts...
ISPASS
2010
IEEE
15 years 4 months ago
2010
IEEE
—In the past ten years, computer architecture has seen a paradigm shift from emphasizing single thread performance to energy efficient, throughput oriented, chip multiprocessors...
TCAD
2008
14 years 8 months ago
2008
The design of MultiProcessor Systems-on-Chip (MPSoC) emphasizes intellectual-property (IP)-based communication-centric approaches. Therefore, for the optimization of the MPSoC inte...