Sciweavers

422 search results - page 5 / 85
» Application mapping for chip multiprocessors
Sort
View
MICRO
2010
IEEE
173views Hardware» more  MICRO 2010»
14 years 7 months ago
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing ha...
Eric S. Chung, Peter A. Milder, James C. Hoe, Ken ...
DAC
2001
ACM
15 years 10 months ago
Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip
We present a design flow for the generation of application-specific multiprocessor architectures. In the flow, architectural parameters are first extracted from a high-level syste...
Damien Lyonnard, Sungjoo Yoo, Amer Baghdadi, Ahmed...
ISCA
2008
IEEE
89views Hardware» more  ISCA 2008»
15 years 4 months ago
Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors
Within-die process variation causes individual cores in a Chip Multiprocessor (CMP) to differ substantially in both static power consumed and maximum frequency supported. In this ...
Radu Teodorescu, Josep Torrellas
ASPDAC
2009
ACM
117views Hardware» more  ASPDAC 2009»
15 years 2 months ago
Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications
– The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Mo...
Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi
HPCA
2005
IEEE
15 years 10 months ago
Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications
In this paper, we study the instruction cache miss behavior of four modern commercial applications (a database workload, TPC-W, SPECjAppServer2002 and SPECweb99). These applicatio...
Lawrence Spracklen, Yuan Chou, Santosh G. Abraham