422 search results - page 68 / 85 » Application mapping for chip multiprocessors |
147
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CASES
2004
ACM
15 years 11 months ago
2004
ACM
As on-chip networks become prevalent in multiprocessor systemson-a-chip and multi-core processors, they will be an integral part of the design flow of such systems. With power in...
132
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CASES
2001
ACM
15 years 9 months ago
2001
ACM
Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory System-on-a-Chip implementation. These overheads are observed in terms of loc...
154
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ANCS
2005
ACM
15 years 11 months ago
2005
ACM
Network processors (NPs) promise a flexible, programmable packet processing infrastructure for network systems. To make full use of the capabilities of network processors, it is ...
281
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CISIS
2010
IEEE
14 years 9 months ago
2010
IEEE
Work-stealing is the todays algorithm of choice for dynamic load-balancing of irregular parallel applications on multiprocessor systems. We have evaluated the algorithm’s effic...
158
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DATE
2010
IEEE
15 years 11 months ago
2010
IEEE
—In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System onChip (SoC) application. We present several design choices and focus on...