422 search results - page 71 / 85 » Application mapping for chip multiprocessors |
DSD
2009
IEEE
15 years 1 months ago
2009
IEEE
Modern systems are able to put two or more processors on the same die (Chip Multiprocessors, CMP), each with its private caches, while the last level caches can be either private ...
DSD
2006
IEEE
15 years 1 months ago
2006
IEEE
We present a performance-oriented refinement approach that refines a perfectly synchronous communication model onto Network-on-Chip (NoC) communication. We first identify four bas...
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DAC
2007
ACM
15 years 10 months ago
2007
ACM
Programming multi-processor systems-on-chip (MPSoC) involves partitioning and mapping of sequential reference code onto multiple parallel processing elements. The immense potentia...
ERSA
2006
14 years 11 months ago
2006
Reconfigurable supercomputing (RSC) combines programmable logic chips with high performance microprocessors, all communicating over a high bandwidth, low latency interconnection n...
CODES
2009
IEEE
15 years 4 months ago
2009
IEEE
Kahn Process Networks is an appealing model of computation for programming and mapping applications onto multi-processor platforms. Autonomous processes communicate through unboun...