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» Application mapping for chip multiprocessors
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ISCA
2010
IEEE
222views Hardware» more  ISCA 2010»
14 years 11 months ago
Cohesion: a hybrid memory model for accelerators
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
John H. Kelm, Daniel R. Johnson, William Tuohy, St...
DT
2000
88views more  DT 2000»
14 years 9 months ago
Postsilicon Validation Methodology for Microprocessors
f abstraction as applicable to break the problem's complexity, and innovating better techniques to address complexity of new microarchitectural features. Validation techniques...
Hemant G. Rotithor
77
Voted
PVLDB
2008
123views more  PVLDB 2008»
14 years 9 months ago
Efficient implementation of sorting on multi-core SIMD CPU architecture
Sorting a list of input numbers is one of the most fundamental problems in the field of computer science in general and high-throughput database applications in particular. Althou...
Jatin Chhugani, Anthony D. Nguyen, Victor W. Lee, ...
80
Voted
DSD
2010
IEEE
112views Hardware» more  DSD 2010»
14 years 8 months ago
Re-NUCA: Boosting CMP Performance Through Block Replication
— Chip Multiprocessor (CMP) systems have become the reference architecture for designing micro-processors, thanks to the improvements in semiconductor nanotechnology that have co...
Pierfrancesco Foglia, Cosimo Antonio Prete, Marco ...
ISCA
2011
IEEE
365views Hardware» more  ISCA 2011»
14 years 1 months ago
Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees
Today’s chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specia...
Boris Grot, Joel Hestness, Stephen W. Keckler, Onu...