422 search results - page 8 / 85 » Application mapping for chip multiprocessors |
71
Voted
IJPP
2010
14 years 8 months ago
2010
In this paper, we define the problem of spatial mapping. We present reasons why performing spatial mappings at run-time is both necessary and desirable. We propose what is—to ou...
ICCAD
2008
IEEE
15 years 6 months ago
2008
IEEE
— As transistor sizes continue to shrink and the number of transistors per chip keeps increasing, chip multiprocessors (CMPs) are becoming a promising alternative to remain on th...
CAL
2002
14 years 9 months ago
2002
Global communication costs in future single-chip multiprocessors will increase linearly with distance. In this paper, we revisit the issues of locality and load balance in order to...
ASPLOS
1998
ACM
15 years 1 months ago
1998
ACM
Thread-level speculation is a technique that enables parallel execution of sequential applications on a multiprocessor. This paper describes the complete implementation of the sup...
96
Voted
ERSA
2007
14 years 11 months ago
2007
- Even though state-of-the-art FPGAs present new opportunities in exploring low-cost high-performance architectures for floating-point scientific applications, they also pose serio...