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JPDC
2011
129views more  JPDC 2011»
14 years 6 months ago
Static timing analysis for modeling QoS in networks-on-chip
Networks-on-chip (NoCs) are used in a growing number of SoCs and multi-core processors. Because messages compete for the NoC’s shared resources, quality of service and resource ...
Evgeni Krimer, Isaac Keslassy, Avinoam Kolodny, Is...
JSS
2010
120views more  JSS 2010»
14 years 9 months ago
An evaluation of timed scenario notations
There is a general consensus on the importance of good Requirements Engineering (RE) for achieving high quality software. The modeling and analysis of requirements have been the m...
Jameleddine Hassine, Juergen Rilling, Rachida Dsso...
QEST
2010
IEEE
14 years 9 months ago
Fortuna: Model Checking Priced Probabilistic Timed Automata
We introduce Fortuna, the first tool for model checking priced probabilistic timed automata (PPTAs). Fortuna can handle the combination of real-time, probabilistic and cost feature...
Jasper Berendsen, David N. Jansen, Frits W. Vaandr...
HPCA
2007
IEEE
15 years 11 months ago
Illustrative Design Space Studies with Microarchitectural Regression Models
We apply a scalable approach for practical, comprehensive design space evaluation and optimization. This approach combines design space sampling and statistical inference to ident...
Benjamin C. Lee, David M. Brooks
118
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RTSS
2005
IEEE
15 years 4 months ago
Event Count Automata: A State-Based Model for Stream Processing Systems
Recently there has been a growing interest in models and methods targeted towards the (co)design of stream processing applications; e.g. those for audio/video processing. Streams ...
Samarjit Chakraborty, Linh T. X. Phan, P. S. Thiag...