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» Application of Reduce Order Modeling to Time Parallelization
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129
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ICML
2009
IEEE
16 years 4 months ago
Large-scale deep unsupervised learning using graphics processors
The promise of unsupervised learning methods lies in their potential to use vast amounts of unlabeled data to learn complex, highly nonlinear models with millions of free paramete...
Rajat Raina, Anand Madhavan, Andrew Y. Ng
ISCAS
2008
IEEE
120views Hardware» more  ISCAS 2008»
15 years 9 months ago
A hybrid CMOS APS pixel for wide-dynamic range imaging applications
— In this paper, a new hybrid photodiode-photogate (HPDPG) CMOS APS pixel for high-dynamic range imaging applications is presented. The HPDPG pixel composes of a biased photogate...
Suat U. Ay
125
Voted
ICPADS
2007
IEEE
15 years 9 months ago
Federated clusters using the transparent remote Execution (TREx) environment
- Due to the increasing complexity of scientific models, large-scale simulation tools often require a critical amount of computational power to produce results in a reasonable amou...
Richert Wang, Enrique Cauich, Isaac D. Scherson
VISUALIZATION
2005
IEEE
15 years 9 months ago
Rendering Tetrahedral Meshes with Higher-Order Attenuation Functions for Digital Radiograph Reconstruction
This paper presents a novel method for computing simulated x-ray images, or DRRs (digitally reconstructed radiographs), of tetrahedral meshes with higher-order attenuation functio...
Ofri Sadowsky, Jonathan D. Cohen, Russell H. Taylo...
ICCAD
2007
IEEE
113views Hardware» more  ICCAD 2007»
15 years 9 months ago
The FAST methodology for high-speed SoC/computer simulation
— This paper describes the FAST methodology that enables a single FPGA to accelerate the performance of cycle-accurate computer system simulators modeling modern, realistic SoCs,...
Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Pa...