Sciweavers

3171 search results - page 154 / 635
» Application of Reduce Order Modeling to Time Parallelization
Sort
View
HPCC
2009
Springer
15 years 8 months ago
On the Performance of Commit-Time-Locking Based Software Transactional Memory
Compared with lock-based synchronization techniques, Software Transactional Memory (STM) can significantly improve the programmability of multithreaded applications. Existing res...
Zhengyu He, Bo Hong
ICCS
2003
Springer
15 years 8 months ago
A Performance Prediction Framework for Scientific Applications
This work presents a performance modeling framework, developed by the Performance Modeling and Characterization (PMaC) Lab at the San Diego Supercomputer Center, that is faster tha...
Laura Carrington, Allan Snavely, Xiaofeng Gao, Nic...
118
Voted
APSEC
2004
IEEE
15 years 7 months ago
Assigning Tasks in a 24-Hour Software Development Model
With the advent of globalization and the Internet, the concept of global software development is gaining ground. The global development model opens up the possibility of 24-hour s...
Pankaj Jalote, Gourav Jain
HIPC
2009
Springer
15 years 1 months ago
Fast checkpointing by Write Aggregation with Dynamic Buffer and Interleaving on multicore architecture
Large scale compute clusters continue to grow to ever-increasing proportions. However, as clusters and applications continue to grow, the Mean Time Between Failures (MTBF) has redu...
Xiangyong Ouyang, Karthik Gopalakrishnan, Tejus Ga...
DATE
1999
IEEE
172views Hardware» more  DATE 1999»
15 years 7 months ago
An Object-Based Executable Model for Simulation of Real-Time Hw/Sw Systems
This paper describes a simulation technique for RealTime Hw/Sw systems based on an object executable model. It allows designers to seamlessly estimate and verify their solutions f...
Olivier Pasquier, Jean Paul Calvez