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» Application of Reduce Order Modeling to Time Parallelization
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169
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ET
2010
113views more  ET 2010»
15 years 27 days ago
Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study
Modern mixed-signal/RF circuits with a digital calibration capability could achieve significant performance improvement through calibration. However, the calibration process often ...
Hsiu-Ming Chang, Kuan-Yu Lin, Kwang-Ting (Tim) Che...
131
Voted
PAAMS
2010
Springer
15 years 1 months ago
A GPU-Based Multi-agent System for Real-Time Simulations
The huge number of cores existing in current Graphics Processor Units (GPUs) provides these devices with computing capabilities that can be exploited by distributed applications. I...
Guillermo Vigueras, Juan M. Orduña, Miguel ...
120
Voted
SIGSOFT
2007
ACM
16 years 4 months ago
Parallel test generation and execution with Korat
We present novel algorithms for parallel testing of code that takes structurally complex test inputs. The algorithms build on the Korat algorithm for constraint-based generation o...
Sasa Misailovic, Aleksandar Milicevic, Nemanja Pet...
148
Voted
ICS
1993
Tsinghua U.
15 years 7 months ago
Dynamic Control of Performance Monitoring on Large Scale Parallel Systems
Performance monitoring of large scale parallel computers creates a dilemma: we need to collect detailed information to find performance bottlenecks, yet collecting all this data ...
Jeffrey K. Hollingsworth, Barton P. Miller
172
Voted
JSSPP
1995
Springer
15 years 7 months ago
A Microeconomic Scheduler for Parallel Computers
We describe a scheduler based on the microeconomic paradigm for scheduling on-line a set of parallel jobs in a multiprocessor system. In addition to increasing the system throughpu...
Ion Stoica, Hussein M. Abdel-Wahab, Alex Pothen