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» Application of Reduce Order Modeling to Time Parallelization
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123
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DATE
2002
IEEE
84views Hardware» more  DATE 2002»
15 years 8 months ago
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications
Microprocessors are today getting more and more inefficient for a growing range of applications. Its principles -The Von Neumann paradigm[3]- based on the sequential execution of ...
Gilles Sassatelli, Lionel Torres, Pascal Benoit, T...
106
Voted
IPPS
2003
IEEE
15 years 9 months ago
Miss Penalty Reduction Using Bundled Capacity Prefetching in Multiprocessors
While prefetch has proven itself useful for reducing cache misses in multiprocessors, traffic is often increased due to extra unused prefetch data. Prefetching in multiprocessors...
Dan Wallin, Erik Hagersten
116
Voted
IPPS
2008
IEEE
15 years 10 months ago
Symbolic expression analysis for compiled communication
Enabling circuit switching in multiprocessor systems has the potential to achieve more efficient communication with lower cost compared to packet/wormhole switching. However, in ...
Shuyi Shao, Yu Zhang, Alex K. Jones, Rami G. Melhe...
122
Voted
WSC
2004
15 years 5 months ago
Modeling and Simulation of Complex Systems with Cell-DEVS
Cell-DEVS enables efficient execution of complex cellular models. The goal of Cell-DEVS is to build discrete-event cell spaces, improving their definition by making the timing spe...
Gabriel A. Wainer
151
Voted
CCGRID
2011
IEEE
14 years 7 months ago
Network-Friendly One-Sided Communication through Multinode Cooperation on Petascale Cray XT5 Systems
—One-sided communication is important to enable asynchronous communication and data movement for Global Address Space (GAS) programming models. Such communication is typically re...
Xinyu Que, Weikuan Yu, Vinod Tipparaju, Jeffrey S....