3171 search results - page 206 / 635 » Application of Reduce Order Modeling to Time Parallelization |
125
Voted
ASPDAC
2007
ACM
15 years 7 months ago
2007
ACM
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
152
Voted
CGF
2005
15 years 3 months ago
2005
Current surface-based methods for interactive freeform editing of high resolution 3D models are very powerful, but at the same time require a certain minimum tessellation or sampl...
145
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IPPS
1998
IEEE
15 years 8 months ago
1998
IEEE
Recent advances in FPGA technologies allow to configure the RAM-based FPGA devices in a reduced time as an effective support for real-time applications. The physical dimensions of ...
158
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SC
2005
ACM
15 years 9 months ago
2005
ACM
In contrast to traditional terascale simulations that have known, fixed data inputs, dynamic data-driven (DDD) applications are characterized by unknown data and informed by dynam...
126
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ICS
2009
Tsinghua U.
15 years 10 months ago
2009
Tsinghua U.
Iterative stencil loops (ISLs) are used in many applications and tiling is a well-known technique to localize their computation. When ISLs are tiled across a parallel architecture...