3171 search results - page 211 / 635 » Application of Reduce Order Modeling to Time Parallelization |
129
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DATE
2006
IEEE
15 years 9 months ago
2006
IEEE
Temporal partitioning techniques are useful to implement large and complex applications, which can be split into partitions in FPGA devices. In order to minimize resources, each o...
117
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KDD
2005
ACM
16 years 4 months ago
2005
ACM
Computer architects utilize simulation tools to evaluate the merits of a new design feature. The time needed to adequately evaluate the tradeoffs associated with adding any new fe...
123
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CADE
1992
Springer
15 years 7 months ago
1992
Springer
Theorem provers based on model elimination have exhibited extremely high inference rates but have lacked a redundancy control mechanism such as subsumption. In this paper we repor...
157
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ICPPW
2009
IEEE
15 years 1 months ago
2009
IEEE
Vehicular Delay-Tolerant Networks (VDTNs) are an application of the Delay-Tolerant Network (DTN) concept, where the movement of vehicles and their message relaying service is used ...
127
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CVPR
2009
IEEE
16 years 11 months ago
2009
IEEE
Many vision and graphics problems such as relighting,
structured light scanning and photometric stereo, need im-
ages of a scene under a number of different illumination
conditi...