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» Application of Reduce Order Modeling to Time Parallelization
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ASPDAC
2004
ACM
120views Hardware» more  ASPDAC 2004»
15 years 9 months ago
Compiler based exploration of DSP energy savings by SIMD operations
— The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting their special architecture features. Beside the ...
Markus Lorenz, Peter Marwedel, Thorsten Dräge...
VLSID
2002
IEEE
115views VLSI» more  VLSID 2002»
16 years 4 months ago
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits
We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is...
Irith Pomeranz, Sudhakar M. Reddy
CCGRID
2008
IEEE
15 years 5 months ago
A Probabilistic Model to Analyse Workflow Performance on Production Grids
Production grids are complex and highly variable systems whose behavior is not well understood and difficult to anticipate. The goal of this study is to estimate the impact of the ...
Tristan Glatard, Johan Montagnat, Xavier Pennec
GECCO
2004
Springer
137views Optimization» more  GECCO 2004»
15 years 9 months ago
Achieving Shorter Search Times in Voice Conversion Using Interactive Evolution
We have already proposed using evolutionary computation to adjust the voice quality conversion parameters, and we have reported that this approach produces results that are not onl...
Yuji Sato
INFOVIS
2005
IEEE
15 years 9 months ago
Importance-Driven Visualization Layouts for Large Time Series Data
Time series are an important type of data with applications in virtually every aspect of the real world. Often a large number of time series have to be monitored and analyzed in p...
Ming C. Hao, Umeshwar Dayal, Daniel A. Keim, Tobia...