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» Application of Reduce Order Modeling to Time Parallelization
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DSD
2010
IEEE
110views Hardware» more  DSD 2010»
15 years 4 months ago
A Predictable Multiprocessor Design Flow for Streaming Applications with Dynamic Behaviour
—The design of new embedded systems is getting more and more complex as more functionality is integrated into these systems. To deal with the design complexity, a predictable des...
Sander Stuijk, Marc Geilen, Twan Basten
HPCA
2005
IEEE
16 years 4 months ago
Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors
Dynamic voltage and frequency scaling (DVFS) is a widely-used method for energy-efficient computing. In this paper, we present a new intra-task online DVFS scheme for multiple clo...
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas...
SAT
2005
Springer
142views Hardware» more  SAT 2005»
15 years 9 months ago
Optimizations for Compiling Declarative Models into Boolean Formulas
Advances in SAT solver technology have enabled many automated analysis and reasoning tools to reduce their input problem to a SAT problem, and then to use an efficient SAT solver ...
Darko Marinov, Sarfraz Khurshid, Suhabe Bugrara, L...
EUROPAR
2009
Springer
15 years 10 months ago
Steady-State for Batches of Identical Task Trees
Abstract In this paper, we focus on the problem of scheduling batches of identical task graphs on a heterogeneous platform, when the task graph consists in a tree. We rely on stead...
Sékou Diakité, Loris Marchal, Jean-M...
GRID
2010
Springer
15 years 1 months ago
Dynamic Partitioning of GATE Monte-Carlo Simulations on EGEE
Abstract The EGEE grid offers the necessary infrastructure and resources for reducing the running time of particle tracking Monte-Carlo applications like GATE. However, efforts are...
Sorina Camarasu-Pop, Tristan Glatard, Jakub T. Mos...