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» Application of Reduce Order Modeling to Time Parallelization
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SAC
2006
ACM
15 years 10 months ago
Building the functional performance model of a processor
In this paper, we present an efficient procedure for building a piecewise linear function approximation of the speed function of a processor with hierarchical memory structure. Th...
Alexey L. Lastovetsky, Ravi Reddy, Robert Higgins
EMSOFT
2008
Springer
15 years 5 months ago
On the interplay of dynamic voltage scaling and dynamic power management in real-time embedded applications
Dynamic Voltage Scaling (DVS) and Dynamic Power Management (DPM) are two popular techniques commonly employed to save energy in real-time embedded systems. DVS policies aim at red...
Vinay Devadas, Hakan Aydin
ICML
2006
IEEE
16 years 5 months ago
Nightmare at test time: robust learning by feature deletion
When constructing a classifier from labeled data, it is important not to assign too much weight to any single input feature, in order to increase the robustness of the classifier....
Amir Globerson, Sam T. Roweis
GECCO
2004
Springer
128views Optimization» more  GECCO 2004»
15 years 9 months ago
An Informed Operator Based Genetic Algorithm for Tuning the Reaction Rate Parameters of Chemical Kinetics Mechanisms
A reduced model technique based on a reduced number of numerical simulations at a subset of operating conditions for a perfectly stirred reactor is developed in order to increase t...
Lionel Elliott, Derek B. Ingham, Adrian G. Kyne, N...
SERA
2005
Springer
15 years 10 months ago
A Design and Test Technique for Embedded Software
In recent years, embedded systems have become so complex and the development time to market is required to be shorter than before. As embedded systems include more functions for n...
Byeongdo Kang, Young-Jik Kwon, Roger Y. Lee