3171 search results - page 283 / 635 » Application of Reduce Order Modeling to Time Parallelization |
135
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FPGA
1998
ACM
15 years 8 months ago
1998
ACM
Current reconfigurable systems suffer from a significant overhead due to the time it takes to reconfigure their hardware. In order to deal with this overhead, and increase the com...
120
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PADS
2003
ACM
15 years 9 months ago
2003
ACM
This paper presents Maya, a multi-paradigm, scalable and extensible network modeling framework for emulating distributed applications. A novel three-tier architecture is proposed ...
174
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RTSS
2003
IEEE
15 years 9 months ago
2003
IEEE
Data caches are essential in modern processors, bridging the widening gap between main memory and processor speeds. However, they yield very complex performance models, which make...
123
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SAMOS
2004
Springer
15 years 9 months ago
2004
Springer
Abstract. Loop unrolling plays an important role in compilation for Reconfigurable Processing Units (RPUs) as it exposes operator parallelism and enables other transformations (e.g...
129
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APCSAC
2005
IEEE
15 years 10 months ago
2005
IEEE
In order to enhance the performance of a computer, most modern processors use superscalar architecture and raise the clock frequency. Superscalar architecture can execute more than...