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» Application of Reduce Order Modeling to Time Parallelization
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ACL
1997
15 years 5 months ago
A Word-to-Word Model of Translational Equivalence
Many multilingual NLP applications need to translate words between different languages, but cannot afford the computational expense of inducing or applying a full translation mode...
I. Dan Melamed
DATE
2008
IEEE
124views Hardware» more  DATE 2008»
15 years 11 months ago
Resistive Bridging Fault Simulation of Industrial Circuits
We report the successful application of a resistive bridging fault (RBF) simulator to industrial benchmark circuits. Despite the slowdown due to the consideration of the sophistic...
Piet Engelke, Ilia Polian, Jürgen Schlöf...
EUROSYS
2010
ACM
15 years 10 months ago
XCPU3: Workload Distribution and Aggregation
The mainstream adoption of cluster, grid, and most recently cloud computing models have broadened the applicability of parallel programming from scientific communities to the bus...
Pravin Shinde, Eric Van Hensbergen
EUROPAR
2001
Springer
15 years 9 months ago
Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
Toshinori Sato, Itsujiro Arita
MIDDLEWARE
2001
Springer
15 years 9 months ago
Thread Transparency in Information Flow Middleware
Abstract. Existing middleware is based on control-flow centric interaction models such as remote method invocations, poorly matching the structure of applications that process con...
Rainer Koster, Andrew P. Black, Jie Huang, Jonatha...