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» Application of Reduce Order Modeling to Time Parallelization
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ISCA
1994
IEEE
129views Hardware» more  ISCA 1994»
15 years 8 months ago
Impact of Sharing-Based Thread Placement on Multithreaded Architectures
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
Radhika Thekkath, Susan J. Eggers
RTAS
2008
IEEE
15 years 11 months ago
Physical Assembly Mapper: A Model-Driven Optimization Tool for QoS-Enabled Component Middleware
This paper provides four contributions to the study of optimization techniques for component-based distributed realtime and embedded (DRE) systems. First, we describe key challeng...
Krishnakumar Balasubramanian, Douglas C. Schmidt
COLCOM
2009
IEEE
15 years 9 months ago
An analytical study of GWAP-based geospatial tagging systems
—Geospatial tagging (geotagging) is an emerging and very promising application that can help users find a wide variety of location-specific information, and facilitate the deve...
Ling-Jyh Chen, Yu-Song Syu, Bo-Chun Wang, Wang-Chi...
SPIN
2007
Springer
15 years 10 months ago
Model Extraction for ARINC 653 Based Avionics Software
One of the most exciting and promising approaches to ensure the correctness of critical systems is software model checking, which considers real code, written with standard program...
Pedro de la Cámara, María-del-Mar Ga...
GRID
2008
Springer
15 years 5 months ago
Rescheduling co-allocation requests based on flexible advance reservations and processor remapping
Large-scale computing environments, such as TeraGrid, Distributed ASCI Supercomputer (DAS), and Grid’5000, have been using resource co-allocation to execute applications on mult...
Marco Aurélio Stelmar Netto, Rajkumar Buyya