3171 search results - page 331 / 635 » Application of Reduce Order Modeling to Time Parallelization |
155
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FCCM
2008
IEEE
15 years 11 months ago
2008
IEEE
High-Level Languages (HLLs) for FPGAs (FieldProgrammable Gate Arrays) facilitate the use of reconfigurable computing resources for application developers by using familiar, higher...
117
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ESCIENCE
2006
IEEE
15 years 10 months ago
2006
IEEE
This paper describes the development and use of an extensible service provider toolkit (ESP) for an Earth Science service-oriented architecture (SOA). Grid-enabled Earth Science a...
141
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ICIP
2005
IEEE
16 years 6 months ago
2005
IEEE
This paper presents an efficient and scalable coding scheme for transmitting a stream of 3D models extracted from a video of a static scene. As in classical model-based video codi...
121
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DATE
2006
IEEE
15 years 10 months ago
2006
IEEE
In many computer systems with large data computations, the delay of memory access is one of the major performance bottlenecks. In this paper, we propose an enhanced field remappi...
112
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ICCAD
2004
IEEE
16 years 1 months ago
2004
IEEE
We propose two new FPGA routing switch designs that are programmable to operate in three different modes: highspeed, low-power or sleep. High-speed mode provides similar power an...