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» Application of Reduce Order Modeling to Time Parallelization
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144
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IPPS
2010
IEEE
15 years 2 months ago
Dynamic analysis of the relay cache-coherence protocol for distributed transactional memory
Transactional memory is an alternative programming model for managing contention in accessing shared in-memory data objects. Distributed transactional memory (TM) promises to alle...
Bo Zhang, Binoy Ravindran
TIME
2009
IEEE
15 years 11 months ago
Model Checking CTL is Almost Always Inherently Sequential
The model checking problem for CTL is known to be P-complete (Clarke, Emerson, and Sistla (1986), see Schnoebelen (2002)). We consider fragments of CTL obtained by restricting the...
Olaf Beyersdorff, Arne Meier, Michael Thomas, Heri...
EUROPAR
2001
Springer
15 years 9 months ago
Building TMR-Based Reliable Servers Despite Bounded Input Lifetimes
This paper is on the construction of a server subsystem in a client/server system in an application context where the number of potential clients can be arbitrarily large. The imp...
Paul D. Ezhilchelvan, Jean-Michel Hélary, M...
166
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SCANGIS
2003
15 years 6 months ago
Spatio-Temporal Modeling of Dynamic Phenomena in GIS
Although, most of phenomena change over time, there has been an attempt to model the phenomena of real world assuming a static nature for them. Even when changes occurred in the p...
Saeed Nadi, Mahmoud Reza Delavar
VLSID
2004
IEEE
147views VLSI» more  VLSID 2004»
16 years 5 months ago
Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
Shabbir H. Batterywala, Narendra V. Shenoy