3171 search results - page 361 / 635 » Application of Reduce Order Modeling to Time Parallelization |
179
click to vote
HPCA
2008
IEEE
16 years 4 months ago
2008
IEEE
Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known techniq...
145
click to vote
IPPS
2009
IEEE
15 years 11 months ago
2009
IEEE
Modeling communications in wireless networks is a challenging task since it asks for a simple mathematical object on which efficient algorithms can be designed, but that must also...
158
click to vote
CSB
2003
IEEE
15 years 9 months ago
2003
IEEE
The promise of plentiful data on common human genetic variations has given hope that we will be able to uncover genetic factors behind common diseases that have proven difficult ...
130
click to vote
QEST
2010
IEEE
15 years 2 months ago
2010
IEEE
The importance of the order two Markovian arrival process (MAP(2)) comes from its compactness, serving either as arrival or service process in applications, and from the nice prope...
125
click to vote
IPPS
2000
IEEE
15 years 8 months ago
2000
IEEE
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...