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» Application of Reduce Order Modeling to Time Parallelization
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HPCC
2007
Springer
15 years 10 months ago
A Low-Power Globally Synchronous Locally Asynchronous FFT Processor
Abstract. Low-power design became crucial with the widespread use of the embedded systems, where a small battery has to last for a long period. The embedded processors need to efï¬...
Yong Li, Zhiying Wang, Jian Ruan, Kui Dai
ICPADS
2002
IEEE
15 years 9 months ago
The Impact of RTS Threshold on IEEE 802.11 MAC Protocol
Wireless technologies and applications received great attention in recent years. The medium access control (MAC) protocol is the main element that determines the efficiency in sha...
Shiann-Tsong Sheu, Tobias Chen, Jenhui Chen, Fun Y...
CLUSTER
2007
IEEE
15 years 8 months ago
A feasibility analysis of power-awareness and energy minimization in modern interconnects for high-performance computing
High-performance computing (HPC) systems consume a significant amount of power, resulting in high operational costs, reduced reliability, and wasting of natural resources. Therefor...
Reza Zamani, Ahmad Afsahi, Ying Qian, V. Carl Hama...
FTTCS
2006
132views more  FTTCS 2006»
15 years 4 months ago
Algorithms and Data Structures for External Memory
Data sets in large applications are often too massive to fit completely inside the computer's internal memory. The resulting input/output communication (or I/O) between fast ...
Jeffrey Scott Vitter
ICPADS
2010
IEEE
15 years 2 months ago
Hybrid Checkpointing for MPI Jobs in HPC Environments
As the core count in high-performance computing systems keeps increasing, faults are becoming common place. Checkpointing addresses such faults but captures full process images ev...
Chao Wang, Frank Mueller, Christian Engelmann, Ste...