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» Application of Reduce Order Modeling to Time Parallelization
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DATE
2010
IEEE
156views Hardware» more  DATE 2010»
15 years 9 months ago
Domain specific architecture for next generation wireless communication
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
Botao Zhang, Hengzhu Liu, Heng Zhao, Fangzheng Mo,...
CASES
2007
ACM
15 years 8 months ago
Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs
Advances in semiconductor technologies have placed MPSoCs center stage as a standard architecture for embedded applications of ever increasing complexity. Efficient utilization of...
Chengmo Yang, Alex Orailoglu
SI3D
1995
ACM
15 years 8 months ago
The Sort-First Rendering Architecture for High-Performance Graphics
Interactive graphics applications have long been challenging graphics system designers by demanding machines that can provide ever increasing polygon rendering performance. Anothe...
Carl Mueller
VL
2008
IEEE
115views Visual Languages» more  VL 2008»
15 years 10 months ago
Flexible visualization of automatic simulation based on structured graph transformation
Visual modeling languages for discrete behavior modeling allow the modeler to describe how systems develop over time during system runs. Models of these languages are the basis fo...
Enrico Biermann, Claudia Ermel, Jonas Hurrelmann, ...
CLUSTER
2004
IEEE
15 years 4 months ago
Resource Management for Ad-Hoc Wireless Networks with Cluster Organization
Boosted by technology advancements, government and commercial interest, ad-hoc wireless networks are emerging as a serious platform for distributed mission-critical applications. G...
Ionut Cardei, Srivatsan Varadarajan, Allalaghatta ...