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» Application of Reduce Order Modeling to Time Parallelization
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DATE
2009
IEEE
138views Hardware» more  DATE 2009»
15 years 11 months ago
Cache aware compression for processor debug support
—During post-silicon processor debugging, we need to frequently capture and dump out the internal state of the processor. Since internal state constitutes all memory elements, th...
Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishna...
AHS
2006
IEEE
142views Hardware» more  AHS 2006»
15 years 10 months ago
On-Chip Evolution Using a Soft Processor Core Applied to Image Recognition
To increase the flexibility of single-chip evolvable hardware systems, we explore possibilities of systems with the evolutionary algorithm implemented in software on an onchip pr...
Kyrre Glette, Jim Torresen, Moritoshi Yasunaga, Yo...
FCCM
2006
IEEE
170views VLSI» more  FCCM 2006»
15 years 7 months ago
An Architecture for Efficient Hardware Data Mining using Reconfigurable Computing Systems
The Apriori algorithm is a fundamental correlation-based data mining kernel used in a variety of fields. The innovation in this paper is a highly parallel custom architecture impl...
Zachary K. Baker, Viktor K. Prasanna
SAS
2007
Springer
126views Formal Methods» more  SAS 2007»
15 years 10 months ago
Hierarchical Pointer Analysis for Distributed Programs
We present a new pointer analysis for use in shared memory programs running on hierarchical parallel machines. The analysis is motivated by the partitioned global address space lan...
Amir Kamil, Katherine A. Yelick
ICDCS
2007
IEEE
15 years 8 months ago
Efficient Backbone Construction Methods in MANETs Using Directional Antennas
In this paper, we consider the issue of constructing an energy-efficient virtual network backbone in mobile ad hoc networks (MANETs) for broadcasting applications using directiona...
Shuhui Yang, Jie Wu, Fei Dai