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» Application of Reduce Order Modeling to Time Parallelization
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GLVLSI
2009
IEEE
125views VLSI» more  GLVLSI 2009»
15 years 7 months ago
Spatial and temporal design debug using partial MaxSAT
Design debug remains one of the major bottlenecks in the VLSI design cycle today. Existing automated solutions strive to aid engineers in reducing the debug effort by identifying ...
Yibin Chen, Sean Safarpour, Andreas G. Veneris, Jo...
136
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ASIAMS
2007
IEEE
15 years 10 months ago
Broadcasting in (n, k)-Arrangement Graph Based on an Optimal Spanning Tree
The tree structure has received much interest as a versatile architecture for a large class of parallel processing applications. Spanning trees in particular are essential tools f...
Jingli Li, Yonghong Xiang, Manli Chen, Yongheng Zh...
131
Voted
SSD
2001
Springer
145views Database» more  SSD 2001»
15 years 8 months ago
Continuous Queries within an Architecture for Querying XML-Represented Moving Objects
The development of spatiotemporal database systems is primarily motivated by applications tracking and presenting mobile objects. Another important trend is the visualization and p...
Thomas Brinkhoff, Jürgen Weitkämper
170
Voted
HPCA
1996
IEEE
15 years 8 months ago
A Comparison of Entry Consistency and Lazy Release Consistency Implementations
This paper compares several implementations of entry consistency (EC) and lazy release consistency (LRC), two relaxed memory models in use with software distributed shared memory ...
Sarita V. Adve, Alan L. Cox, Sandhya Dwarkadas, Ra...
130
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PDCAT
2005
Springer
15 years 9 months ago
LRC-RED: A Self-tuning Robust and Adaptive AQM Scheme
In this paper, we propose a novel active queue management (AQM) scheme based on the Random Early Detection (RED) of the loss ratio and the total sending rate control, called LRC-R...
Naixue Xiong, Yan Yang, Xavier Défago, Yanx...