Sciweavers

3171 search results - page 466 / 635
» Application of Reduce Order Modeling to Time Parallelization
Sort
View
SMA
2010
ACM
171views Solid Modeling» more  SMA 2010»
15 years 3 months ago
Efficient simplex computation for fixture layout design
Designing a fixture layout of an object can be reduced to computing the largest simplex and the resulting simplex is classified using the radius of the largest inscribed ball cent...
Yu Zheng, Ming C. Lin, Dinesh Manocha
139
Voted
HPCA
2002
IEEE
16 years 3 months ago
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay
Cache memories account for a significant fraction of a chip's overall energy dissipation. Recent research advocates using "resizable" caches to exploit cache requir...
Se-Hyun Yang, Michael D. Powell, Babak Falsafi, T....
168
Voted
SP
2008
IEEE
138views Security Privacy» more  SP 2008»
15 years 3 months ago
A performance tuning methodology with compiler support
We have developed an environment, based upon robust, existing, open source software, for tuning applications written using MPI, OpenMP or both. The goal of this effort, which inte...
Oscar Hernandez, Barbara M. Chapman, Haoqiang Jin
123
Voted
EWSN
2007
Springer
16 years 3 months ago
Multithreading Optimization Techniques for Sensor Network Operating Systems
While a multithreading approach provides a convenient sensor application developing environment with automatic control flow and stack managment, it is considered to have a larger d...
Hyoseung Kim, Hojung Cha
157
Voted
ASPLOS
2008
ACM
15 years 5 months ago
Communication optimizations for global multi-threaded instruction scheduling
The recent shift in the industry towards chip multiprocessor (CMP) designs has brought the need for multi-threaded applications to mainstream computing. As observed in several lim...
Guilherme Ottoni, David I. August