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» Application of Reduce Order Modeling to Time Parallelization
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117
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ISCA
2007
IEEE
208views Hardware» more  ISCA 2007»
15 years 9 months ago
Core fusion: accommodating software diversity in chip multiprocessors
This paper presents core fusion, a reconfigurable chip multiprocessor (CMP) architecture where groups of fundamentally independent cores can dynamically morph into a larger CPU, ...
Engin Ipek, Meyrem Kirman, Nevin Kirman, Jos&eacut...
ISSS
2002
IEEE
138views Hardware» more  ISSS 2002»
15 years 8 months ago
An Object-Oriented Design Process for System-on-Chip Using UML
The object-oriented design process has been a hot topic in software development since it will improve product quality and productivity significantly, which is also a major issue i...
Tsuneo Nakata, Akio Matsuda, Minoru Shoji, Shinya ...
134
Voted
VLSID
2004
IEEE
138views VLSI» more  VLSID 2004»
16 years 3 months ago
Synthesis-driven Exploration of Pipelined Embedded Processors
Recent advances on language based software toolkit generation enables performance driven exploration of embedded systems by exploiting the application behavior. There is a need fo...
Prabhat Mishra, Arun Kejariwal, Nikil Dutt
TWC
2008
148views more  TWC 2008»
15 years 3 months ago
ARMA Synthesis of Fading Channels
Computationally scalable and accurate estimation, prediction, and simulation of wireless communication channels is critical to the development of more adaptive transceiver algorith...
Hani Mehrpouyan, Steven D. Blostein
121
Voted
COLCOM
2005
IEEE
15 years 9 months ago
Matching distributed systems to their environment using dissipative structures
In contrast to a large body of theoretical work on computer systems, distributed systems are not idealised constructions, unconstrained by physical world limitations. They must be...
Jim Dowling, Dominik Dahlem, Jan Sacha