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» Application of Reduce Order Modeling to Time Parallelization
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FCCM
1997
IEEE
129views VLSI» more  FCCM 1997»
15 years 7 months ago
The Chimaera reconfigurable functional unit
By strictly separating reconfigurable logic from their host processor, current custom computing systems suffer from a significant communication bottleneck. In this paper we descri...
Scott Hauck, Thomas W. Fry, Matthew M. Hosler, Jef...
116
Voted
ISLPED
1997
ACM
99views Hardware» more  ISLPED 1997»
15 years 7 months ago
Low power data processing by elimination of redundant computations
We suggest a new technique to reduce energy consumption in the processor datapath without sacrificing performance by exploiting operand value locality at run time. Data locality is...
Mir Azam, Paul D. Franzon, Wentai Liu
JSW
2008
99views more  JSW 2008»
15 years 3 months ago
Using Data Mining in MURA Graphic Problems
The MURA phenomenon will result lots of problems in Photomask and TFT-LCD industries as well. In this paper, we designed and developed a MURA related association rules which suitab...
Wen-Hsing Kao, Jason C. Hung, Victoria Hsu
167
Voted
RTS
2010
127views more  RTS 2010»
14 years 10 months ago
Scheduling of hard real-time garbage collection
Automatic memory management or garbage collection greatly simplifies development of large systems. However, garbage collection is usually not used in real-time systems due to the u...
Martin Schoeberl
123
Voted
CVPR
2010
IEEE
15 years 9 months ago
Fast Sparse Representation with Prototypes
Sparse representation has found applications in numerous domains and recent developments have been focused on the convex relaxation of the 0-norm minimization for sparse coding (i...
Jia-Bin Huang, Ming-Hsuan Yang