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» Application of Reduce Order Modeling to Time Parallelization
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VLSID
2009
IEEE
108views VLSI» more  VLSID 2009»
16 years 2 months ago
Metric Based Multi-Timescale Control for Reducing Power in Embedded Systems
Abstract--Digital control for embedded systems often requires low-power, hard real-time computation to satisfy high control-loop bandwidth, low latency, and low-power requirements....
Forrest Brewer, João Pedro Hespanha, Nitin ...
JSS
2010
120views more  JSS 2010»
15 years 12 days ago
An evaluation of timed scenario notations
There is a general consensus on the importance of good Requirements Engineering (RE) for achieving high quality software. The modeling and analysis of requirements have been the m...
Jameleddine Hassine, Juergen Rilling, Rachida Dsso...
HPCA
2006
IEEE
16 years 2 months ago
Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads
With the continuing growth in the amount of genetic data, members of the bioinformatics community are developing a variety of data-mining applications to understand the data and d...
Aamer Jaleel, Matthew Mattina, Bruce L. Jacob
ATAL
2006
Springer
15 years 5 months ago
A technique for reducing normal-form games to compute a Nash equilibrium
We present a technique for reducing a normal-form (aka. (bi)matrix) game, O, to a smaller normal-form game, R, for the purpose of computing a Nash equilibrium. This is done by com...
Vincent Conitzer, Tuomas Sandholm
ICCS
2004
Springer
15 years 7 months ago
Using Runtime Measurements and Historical Traces for Acquiring Knowledge in Parallel Applications
Abstract. A new approach for acquiring knowledge of parallel applications regarding resource usage and for searching similarity on workload traces is presented. The main goal is to...
Luciano José Senger, Marcos José San...