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» Application of Reduce Order Modeling to Time Parallelization
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DATE
2005
IEEE
119views Hardware» more  DATE 2005»
15 years 8 months ago
On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips
Multi-site testing is a popular and effective way to increase test throughput and reduce test costs. We present a test throughput model, in which we focus on wafer testing, and co...
Sandeep Kumar Goel, Erik Jan Marinissen
ICCS
2009
Springer
15 years 9 months ago
Simulating Individual-Based Models of Epidemics in Hierarchical Networks
Current mathematical modeling methods for the spreading of infectious diseases are too simplified and do not scale well. We present the Simulator of Epidemic Evolution in Complex ...
Rick Quax, David A. Bader, Peter M. A. Sloot
ATAL
2004
Springer
15 years 8 months ago
Time-Variant Distributed Agent Matching Applications
The process of pair partnership formation is an important infrastructure for many plausible MAS applications. Each agent evaluates potential partner agents, where each potential m...
David Sarne, Sarit Kraus
ISLPED
2003
ACM
115views Hardware» more  ISLPED 2003»
15 years 8 months ago
Reducing energy and delay using efficient victim caches
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...
ACSC
2002
IEEE
15 years 8 months ago
Reducing Cognitive Overhead on the World Wide Web
HyperScout, a Web application, is an intermediary between a server and a client. It intercepts a page to the client, gathers information on each link, and annotates each link with...
R. J. Witt, S. P. Tyerman