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DFT
1999
IEEE
114views VLSI» more  DFT 1999»
15 years 1 months ago
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM
A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 m logic/embedded DRAM process. It integr...
Markus Rudack, Dirk Niggemeyer
VTS
2003
IEEE
131views Hardware» more  VTS 2003»
15 years 2 months ago
Efficient Implication - Based Untestable Bridge Fault Identifier
: This paper presents a novel, low cost technique based on implications to identify untestable bridging faults in sequential circuits. Sequential symbolic simulation [1] is first p...
Manan Syal, Michael S. Hsiao, Kiran B. Doreswamy, ...
IANDC
2010
84views more  IANDC 2010»
14 years 8 months ago
Underapproximation for model-checking based on universal circuits
For two naturals m, n such that m < n, we show how to construct a circuit C with m inputs and n outputs, that has the following property: for some 0 ≤ k ≤ m, the circuit deï...
Arie Matsliah, Ofer Strichman
TVLSI
2008
133views more  TVLSI 2008»
14 years 9 months ago
Test Data Compression Using Selective Encoding of Scan Slices
We present a selective encoding method that reduces test data volume and test application time for scan testing of Intellectual Property (IP) cores. This method encodes the slices ...
Zhanglei Wang, Krishnendu Chakrabarty
ICCAD
2002
IEEE
112views Hardware» more  ICCAD 2002»
15 years 2 months ago
ATPG-based logic synthesis: an overview
The ultimate goal of logic synthesis is to explore implementation flexibility toward meeting design targets, such as area, power, and delay. Traditionally, such flexibility is exp...
Chih-Wei Jim Chang, Malgorzata Marek-Sadowska