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WSC
1997
15 years 20 days ago
Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
Peter S. Magnusson
IJWIS
2006
126views more  IJWIS 2006»
14 years 11 months ago
Web services on embedded devices
Abstract-- The capabilities of embedded devices such as smartphones are steadily increasing and provide the great flexibility of data access and collaboration while being mobile. F...
Daniel Schall, Marco Aiello, Schahram Dustdar
69
Voted
ASAP
2009
IEEE
143views Hardware» more  ASAP 2009»
15 years 8 months ago
Scalar Processing Overhead on SIMD-Only Architectures
—The Cell processor consists of a general-purpose core and eight cores with a complete SIMD instruction set. Although originally designed for multimedia and gaming, it is current...
Arnaldo Azevedo Filho, Ben H. H. Juurlink
NOSSDAV
2001
Springer
15 years 3 months ago
TCP-real: improving real-time capabilities of TCP over heterogeneous networks
We present a TCP-compatible and -friendly protocol which abolishes three major shortfalls of TCP for reliable multimedia applications over heterogeneous networks: (i) ineffective ...
Chi Zhang, Vassilios Tsaoussidis
COMPSAC
2002
IEEE
15 years 4 months ago
Using RAIC for Dependable On-line Upgrading of Distributed Systems
Redundant Arrays of Independent Components (RAIC) is a technology that uses groups of similar or identical distributed components to provide dependable services [1,2,3]. RAIC allo...
Chang Liu, Debra J. Richardson