Efficiently utilizing off-chip DRAM bandwidth is a critical issue in designing cost-effective, high-performance chip multiprocessors (CMPs). Conventional memory controllers deli...
Reconfigurable Systolic Arrays are a generalization of Systolic Arrays where node operations and interconnections can be redefined even at run time. This flexibility increases the...
The performance features of MEMS transducers allow the development of a new class of small, low-power sensor microsystems which utilize a suite of sensors to support a wide range ...
This paper presents the e-SUIT, a wearable computer incorporated in a traditional business suit. A key feature of the system is an array of input/output devices integrated into th...
Aaron Toney, Barrie Mulley, Bruce H. Thomas, Wayne...
This paper explores hardware-implemented error-detection and security mechanisms embedded as modules in a hardware-level framework called the Reliability and Security Engine (RSE)...
Nithin Nakka, Zbigniew Kalbarczyk, Ravishankar K. ...