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MICRO
2006
IEEE
162views Hardware» more  MICRO 2006»
15 years 4 months ago
Adaptive Caches: Effective Shaping of Cache Behavior to Workloads
We present and evaluate the idea of adaptive processor cache management. Specifically, we describe a novel and general scheme by which we can combine any two cache management alg...
Ranjith Subramanian, Yannis Smaragdakis, Gabriel H...
WWIC
2004
Springer
123views Communications» more  WWIC 2004»
15 years 3 months ago
Experimental Analysis of Heterogeneous Wireless Networks
Packet loss and delay in Internet degrade the quality of requested services like VoIP (Voice over IP) or Video Streaming. In novel network scenarios where wired and wireless connec...
Giulio Iannello, Antonio Pescapè, Giorgio V...
SIGMOD
2007
ACM
196views Database» more  SIGMOD 2007»
15 years 10 months ago
GPUQP: query co-processing using graphics processors
We present GPUQP, a relational query engine that employs both CPUs and GPUs (Graphics Processing Units) for in-memory query co-processing. GPUs are commodity processors traditiona...
Rui Fang, Bingsheng He, Mian Lu, Ke Yang, Naga K. ...
EUROSYS
2007
ACM
15 years 7 months ago
STMBench7: a benchmark for software transactional memory
Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than explicit coarse...
Rachid Guerraoui, Michal Kapalka, Jan Vitek
ISCAS
2007
IEEE
104views Hardware» more  ISCAS 2007»
15 years 4 months ago
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors
Process variation in future technologies can cause severe performance degradation since different parts of the shared Register File (RF) in VLIW processors may operate at various ...
Praveen Raghavan, José L. Ayala, David Atie...