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» Application-Driven Optimization of VLIW Architectures: A Har...
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IPPS
1998
IEEE
13 years 10 months ago
Partitioned Schedules for Clustered VLIW Architectures
This paper presents results on a new approach to partitioning a modulo-scheduled loop for distributed execution on parallel clusters of functional units organized as a VLIW machin...
Marcio Merino Fernandes, Josep Llosa, Nigel P. Top...
EUROMICRO
2000
IEEE
13 years 10 months ago
A Simulink(c)-Based Approach to System Level Design and Architecture Selection
We propose a design flow for low-power and low-cost, data-dominated, embedded systems which tightly integrate different technologies and architectures. We use Mathworks’ Simuli...
Luciano Lavagno, Begoña Pino, Leonardo Mari...
MICRO
2006
IEEE
73views Hardware» more  MICRO 2006»
14 years 7 days ago
Merging Head and Tail Duplication for Convergent Hyperblock Formation
VLIW and EDGE (Explicit Data Graph Execution) architectures rely on compilers to form high-quality hyperblocks for good performance. These compilers typically perform hyperblock f...
Bertrand A. Maher, Aaron Smith, Doug Burger, Kathr...
ISSS
1995
IEEE
87views Hardware» more  ISSS 1995»
13 years 9 months ago
Industrial experience using rule-driven retargetable code generation for multimedia applications
The increasing usage of Application Specific Instruction Set Processors (ASIPs) in audio and video telecommunications has made strong demands on the rapid availability of dedicat...
Clifford Liem, Pierre G. Paulin, Marco Cornero, Ah...
JCP
2008
118views more  JCP 2008»
13 years 6 months ago
Power-efficient Instruction Encoding Optimization for Various Architecture Classes
A huge application domain, in particular, wireless and handheld devices strongly requires flexible and powerefficient hardware with high performance. This can only be achieved with...
Diandian Zhang, Anupam Chattopadhyay, David Kammle...