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FPGA
2005
ACM
107views FPGA» more  FPGA 2005»
15 years 3 months ago
Instruction set extension with shadow registers for configurable processors
Configurable processors are becoming increasingly popular for modern embedded systems (especially for the field-programmable system-on-a-chip). While steady progress has been made...
Jason Cong, Yiping Fan, Guoling Han, Ashok Jaganna...
ARC
2006
Springer
88views Hardware» more  ARC 2006»
15 years 1 months ago
Integrating Custom Instruction Specifications into C Development Processes
Abstract. We describe a new approach for creating hardware description language (HDL) specifications for custom instructions, to form part of the instruction-set architecture (ISA)...
Jack Whitham, Neil C. Audsley
DAC
1997
ACM
15 years 1 months ago
Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign
An experimental set of tools that generate instruction set simulators, assemblers, and disassemblers from a single description was developed to test if retargetable development to...
Mark R. Hartoog, James A. Rowson, Prakash D. Reddy...
CODES
1999
IEEE
15 years 1 months ago
An ASIP design methodology for embedded systems
A well-known challenge during processor design is to obtain the best possible results for a typical target application domain that is generally described as a set of benchmarks. O...
Kayhan Küçükçakar
79
Voted
ISCC
2009
IEEE
210views Communications» more  ISCC 2009»
15 years 4 months ago
Towards a Java bytecodes compiler for Nios II soft-core processor
Reconfigurable computing is one of the most recent research topics in computer science. The Altera™ Nios II soft-core processor can be included in a large set of reconfigurable ...
Willian dos Santos Lima, Renata Spolon Lobato, Ale...