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JCP
2008
118views more  JCP 2008»
14 years 9 months ago
Power-efficient Instruction Encoding Optimization for Various Architecture Classes
A huge application domain, in particular, wireless and handheld devices strongly requires flexible and powerefficient hardware with high performance. This can only be achieved with...
Diandian Zhang, Anupam Chattopadhyay, David Kammle...
ICCD
2002
IEEE
146views Hardware» more  ICCD 2002»
15 years 6 months ago
From ASIC to ASIP: The Next Design Discontinuity
A variety of factors is making it increasingly difficult and expensive to design and manufacture traditional Application Specific Integrated Circuits (ASICs). This has started a s...
Kurt Keutzer, Sharad Malik, A. Richard Newton
IPPS
2000
IEEE
15 years 1 months ago
Augmenting Modern Superscalar Architectures with Configurable Extended Instructions
The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, how...
Xianfeng Zhou, Margaret Martonosi
IPPS
2005
IEEE
15 years 3 months ago
Configuration Steering for a Reconfigurable Superscalar Processor
An architecture for a reconfigurable superscalar processor is described in which some of its execution units are implemented in reconfigurable hardware. The overall configuration ...
Brian F. Veale, John K. Antonio, Monte P. Tull
SAC
2004
ACM
15 years 2 months ago
DSPxPlore: design space exploration methodology for an embedded DSP core
High mask and production costs for the newest CMOS silicon technologies increase the pressure to develop hardware platforms useable for different applications or variants of the s...
Christian Panis, Ulrich Hirnschrott, Gunther Laure...