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CHES
2005
Springer
146views Cryptology» more  CHES 2005»
15 years 10 months ago
AES on FPGA from the Fastest to the Smallest
Two new FPGA designs for the Advanced Encryption Standard (AES) are presented. The first is believed to be the fastest, achieving 25 Gbps throughput using a Xilinx Spartan-III (XC3...
Tim Good, Mohammed Benaissa
ACSAC
2000
IEEE
15 years 8 months ago
Usability Meets Security -The Identity-Manager as Your Personal Security Assistant for the Internet
In today’s applications, most users disregard the security functionality. They do not have the knowledge and/or the motivation to configure or to use the existing security func...
Uwe Jendricke, Daniela Gerd tom Markotten
ASAP
2000
IEEE
125views Hardware» more  ASAP 2000»
15 years 8 months ago
High Level Modeling for Parallel Executions of Nested Loop Algorithms
High level modeling and (quantitative) performance analysis of signal processing systems requires high level models for the applications(algorithms) and the implementations (archi...
Ed F. Deprettere, Edwin Rijpkema, Paul Lieverse, B...
ASAP
2000
IEEE
184views Hardware» more  ASAP 2000»
15 years 8 months ago
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter
Sorting long sequences of keys is a problem that occurs in many different applications. For embedded systems, a uniprocessor software solution is often not applicable due to the l...
Marcus Bednara, Oliver Beyer, Jürgen Teich, R...
CODES
2000
IEEE
15 years 8 months ago
Parameterized system design
Continued growth in chip capacity has led to new methodologies stressing reuse, not only of pre-designed processing components, but even of entire pre-designed architectures. To b...
Tony Givargis, Frank Vahid