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DATE
2003
IEEE
117views Hardware» more  DATE 2003»
15 years 8 months ago
Exploring SW Performance Using SoC Transaction-Level Modeling
This paper presents VISTA, a new methodology and tool dedicated to analyse system level performance by executing full-scale SW application code on a transaction-level model of the...
Imed Moussa, Thierry Grellier, Giang Nguyen
FGCS
2006
113views more  FGCS 2006»
15 years 3 months ago
Performance feature identification by comparative trace analysis
This work introduces a method for instrumenting applications, producing execution traces, and visualizing multiple trace instances to identify performance features. The approach p...
Daniel P. Spooner, Darren J. Kerbyson
ESOP
2005
Springer
15 years 8 months ago
Asserting Bytecode Safety
Abstract. We instantiate an Isabelle/HOL framework for proof carrying code to Jinja bytecode, a downsized variant of Java bytecode featuring objects, inheritance, method calls and ...
Martin Wildmoser, Tobias Nipkow
TC
1998
15 years 2 months ago
Optimizing the Instruction Cache Performance of the Operating System
—High instruction cache hit rates are key to high performance. One known technique to improve the hit rate of caches is to minimize cache interference by improving the layout of ...
Josep Torrellas, Chun Xia, Russell L. Daigle
CCS
2011
ACM
14 years 3 months ago
How to break XML encryption
XML Encryption was standardized by W3C in 2002, and is implemented in XML frameworks of major commercial and open-source organizations like Apache, redhat, IBM, and Microsoft. It ...
Tibor Jager, Somorovsky Juraj