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DFT
2007
IEEE
123views VLSI» more  DFT 2007»
15 years 9 months ago
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols
In the paper, a methodology of developing checkers for communication protocol testing is presented. It was used to develop checker to test IP cores communication protocol implemen...
Martin Straka, Jiri Tobola, Zdenek Kotásek
DATE
2005
IEEE
187views Hardware» more  DATE 2005»
15 years 8 months ago
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
In this paper, the application of a cycle accurate binary translator for rapid prototyping of SoCs will be presented. This translator generates code to run on a rapid prototyping ...
Jürgen Schnerr, Oliver Bringmann, Wolfgang Ro...
ECOOP
2004
Springer
15 years 8 months ago
The Expression Problem Revisited
The expression problem (aka the extensibility problem) refers to a fundamental dilemma of programming: Can your application be structured in such a way that both the data model and...
Mads Torgersen
CODES
2002
IEEE
15 years 8 months ago
Metrics for design space exploration of heterogeneous multiprocessor embedded systems
This paper considers the problem of designing heterogeneous multiprocessor embedded systems. The focus is on a step of the design flow: the definition of innovative metrics for th...
Donatella Sciuto, Fabio Salice, Luigi Pomante, Wil...
DCC
2000
IEEE
15 years 7 months ago
The Skip-Innovation Model for Sparse Images
On sparse images, contiguous runs of identical symbols often occur in the same coding context. This paper proposes a model for efficiently encoding such runs in a twodimensional s...
Paul J. Ausbeck Jr.