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VLSID
2002
IEEE
131views VLSI» more  VLSID 2002»
16 years 3 months ago
Divide-and-Conquer IDDQ Testing for Core-Based System Chips
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
C. P. Ravikumar, Rahul Kumar
103
Voted
VTS
2000
IEEE
95views Hardware» more  VTS 2000»
15 years 8 months ago
DEFUSE: A Deterministic Functional Self-Test Methodology for Processors
1 At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-...
Li Chen, Sujit Dey
171
Voted
GECCO
2008
Springer
172views Optimization» more  GECCO 2008»
15 years 4 months ago
Empirical analysis of a genetic algorithm-based stress test technique
Evolutionary testing denotes the use of evolutionary algorithms, e.g., Genetic Algorithms (GAs), to support various test automation tasks. Since evolutionary algorithms are heuris...
Vahid Garousi
IUI
2012
ACM
13 years 11 months ago
Towards automatic functional test execution
As applications are developed, functional tests ensure they continue to function as expected. Nowadays, functional testing is mostly done manually, with human testers verifying a ...
Pablo Pedemonte, Jalal Mahmud, Tessa Lau
VLSID
2002
IEEE
97views VLSI» more  VLSID 2002»
16 years 3 months ago
Multiple Faults: Modeling, Simulation and Test
We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Salu...