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142
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ICCAD
1995
IEEE
94views Hardware» more  ICCAD 1995»
15 years 7 months ago
Test register insertion with minimum hardware cost
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
Albrecht P. Stroele, Hans-Joachim Wunderlich
155
Voted
ICST
2010
IEEE
15 years 2 months ago
Towards a Testing Methodology for Reactive Systems: A Case Study of a Landing Gear Controller
—In this case study we test a landing gear control system of a military aircraft with the new version of LUTESS, a tool for testing automatically synchronous software. LUTESS req...
Laya Madani, Virginia Papailiopoulou, Ioannis Pari...
116
Voted
DATE
2008
IEEE
122views Hardware» more  DATE 2008»
15 years 10 months ago
Digital bit stream jitter testing using jitter expansion
This paper presents a time-domain jitter expansion technique for high-speed digital bit sequence jitter testing. While jitter expansion has been applied to phase noise measurement...
Hyun Choi, Abhijit Chatterjee
157
Voted
ISSRE
2006
IEEE
15 years 9 months ago
Call Stack Coverage for GUI Test-Suite Reduction
—Graphical user interfaces (GUIs) are used as front ends to most of today’s software applications. The event-driven nature of GUIs presents new challenges for testing. One impo...
Scott McMaster, Atif M. Memon
123
Voted
ETS
2007
IEEE
128views Hardware» more  ETS 2007»
15 years 5 months ago
Selecting Power-Optimal SBST Routines for On-Line Processor Testing
Software-Based Self-Test (SBST) has emerged as an effective strategy for on-line testing of processors integrated in non-safety critical embedded system applications. Among the mo...
Andreas Merentitis, Nektarios Kranitis, Antonis M....