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ISSRE
2010
IEEE
15 years 2 months ago
Pinpointing the Subsystems Responsible for the Performance Deviations in a Load Test
—Large scale systems (LSS) contain multiple subsystems that interact across multiple nodes in sometimes unforeseen and complicated ways. As a result, pinpointing the subsystems t...
Haroon Malik, Bram Adams, Ahmed E. Hassan
ACSAC
2010
IEEE
15 years 2 months ago
A framework for testing hardware-software security architectures
New security architectures are difficult to prototype and test at the design stage. Fine-grained monitoring of the interactions between hardware, the operating system, and applica...
Jeffrey S. Dwoskin, Mahadevan Gomathisankaran, Yu-...
ET
2010
113views more  ET 2010»
15 years 1 months ago
Calibration and Test Time Reduction Techniques for Digitally-Calibrated Designs: an ADC Case Study
Modern mixed-signal/RF circuits with a digital calibration capability could achieve significant performance improvement through calibration. However, the calibration process often ...
Hsiu-Ming Chang, Kuan-Yu Lin, Kwang-Ting (Tim) Che...
ICCAD
2006
IEEE
134views Hardware» more  ICCAD 2006»
16 years 27 days ago
A delay fault model for at-speed fault simulation and test generation
We describe a transition fault model, which is easy to simulate under test sequences that are applied at-speed, and provides a target for the generation of at-speed test sequences...
Irith Pomeranz, Sudhakar M. Reddy
ETS
2006
IEEE
110views Hardware» more  ETS 2006»
15 years 10 months ago
Deterministic Logic BIST for Transition Fault Testing
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
Valentin Gherman, Hans-Joachim Wunderlich, Jü...