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120
Voted
DATE
2009
IEEE
136views Hardware» more  DATE 2009»
15 years 10 months ago
A novel approach to entirely integrate Virtual Test into test development flow
– In this paper, we present an open architecture Virtual Test Environment (VTE) which can be easily integrated into various modularized Automatic Test Systems (ATS) compliant to ...
Ping Lu, Daniel Glaser, Gürkan Uygur, Klaus H...
ISQED
2003
IEEE
85views Hardware» more  ISQED 2003»
15 years 8 months ago
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanja...
112
Voted
ECBS
2010
IEEE
151views Hardware» more  ECBS 2010»
15 years 8 months ago
Generating Test Plans for Acceptance Tests from UML Activity Diagrams
The Unified Modeling Language (UML) is the standard to specify the structure and behaviour of software systems. The created models are a constitutive part of the software speci...
Andreas Heinecke, Tobias Brückmann, Tobias Gr...
121
Voted
DATE
2008
IEEE
86views Hardware» more  DATE 2008»
15 years 9 months ago
Test Scheduling for Wafer-Level Test-During-Burn-In of Core-Based SoCs
Abstract—Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testi...
Sudarshan Bahukudumbi, Krishnendu Chakrabarty, Ric...
VTS
2003
IEEE
81views Hardware» more  VTS 2003»
15 years 8 months ago
Test Resource Partitioning and Optimization for SOC Designs
1 We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the ai...
Erik Larsson, Hideo Fujiwara