3256 search results - page 22 / 652 » Applications of Formal Methods to System Design and Verifica... |
SECURWARE
2007
IEEE
15 years 3 months ago
2007
IEEE
The paper discusses an experience in using a realtime UML/SysML profile and a formal verification toolkit to check a secure group communication system against temporal requirement...
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
Choosing the right methodology is a significant step towards successful VLSI designs. Traditional methodologies and tools are no longer adequate to handle large and complex design...
64
Voted
FMCAD
2000
Springer
15 years 1 months ago
2000
Springer
Abstract. Model checking is an automated approach to the formal verification of hardware and software. To allow model checking tools to be used by the hardware or software designer...
73
Voted
CAV
2005
Springer
15 years 3 months ago
2005
Springer
79
Voted
FM
2006
Springer
15 years 1 months ago
2006
Springer
Design patterns are usually described in terms of instances. Templates describe sentences of some language with a particular form, generate sentences upon instantiation, and can be...